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The Art of Pointing: Why the 4004 RAM management will make you question your sanity

Posted: 26 Apr 2026, 17:14
by Jaime Clot
If you are used to modern architectures where you simply "store a value in an address," the Intel 4004 is here to politely remind you that life was not always this easy. In the 1971 world of the 4004, accessing RAM is more like a ritual than a command.

The "SRC" Ritual: Look, but don't touch (yet)

In a modern CPU, you might do something like MOV [0x123], AL. Simple. Direct. Boring.

The 4004 doesn't have enough pins or "mental capacity" for that. To talk to RAM, you first use DCL (Designate Command Line) to select the RAM bank, and then SRC (Send Register Control) to load the RAM address context. Think of it as pointing your finger at a specific spot in a massive warehouse and shouting:
"I'm looking at YOU, bank 2, chip 1, register 0, character 12!"

Wait... Bank? Chip? Character? Let's decode the 1971 hierarchy:

To understand why DCL + SRC exist, you have to visualize how the 4001/4002/4003 chipset actually sits on the board:
  • Bank: The highest level of selection. You can have multiple RAM banks, selected via the CM-RAM lines using DCL. It's like choosing which "room" of the warehouse you are entering.
  • Chip: Each selected bank can contain up to 4 RAM chips (Intel 4002). You are now picking a specific physical IC.
  • Register: Inside each 4002 chip, there are 4 registers.
  • Character: Each register has 16 main 4-bit characters (nibbles).
Once bank selection is latched with DCL (until changed by another DCL) and the address context is sent with SRC (which remains valid until the next SRC), the CPU "remembers" that RAM context. Only then can you actually move data.

Workbench sidebar: the instruction cheat-sheet (built-in)

At this point in the story, I usually glance at my dedicated workbench view: a full Intel 4004 instruction list with short descriptions of what each opcode does. It keeps the "ritual" honest — especially when you are mentally juggling bank/chip/register/character layers.


SCREENSHOT: Instruction reference panel / form in Quadium
WRM00.jpg
WRM00.jpg (58.79 KiB) Viewed 53 times

This is the screen I use as a quick decoder while stepping through code: mnemonics, encoding context, and plain-English intent in one place.

Strange Instruction Family of the Year: WRM/RDM + WRx/RDx

After the DCL + SRC dance, you gain access to data. But even then, the 4004 handles RAM like a neurotic librarian:
  • WRM (Write RAM character): Writes the Accumulator to the selected main Character.
  • RDM (Read RAM character): Reads the selected main Character into the Accumulator.
  • WR0-WR3: Write one of the 4 Status Characters of the selected register.
  • RD0-RD3: Read one of those 4 Status Characters.
Note: ADM / SBM also operate on the same selected main character (add/subtract with carry/borrow), not only plain read/write.

The "Serious" Engineering Joke: The 4004 doesn't just store your numbers; it stores your numbers' "feelings." Every 16-character RAM register has 4 extra "Status" nibbles. It's like having a spreadsheet where every row has 4 hidden sticky notes that require a special, different pen to read/write.

Why was it designed this way?

It wasn't for masochism. The 4004 was born for calculators. The 16 main Characters held digits (mantissa-like payload), while the 4 Status Characters were ideal for metadata such as sign, decimal position, exponent-related info, or per-register flags.

It's a highly optimized, application-specific mess that we have faithfully replicated in Quadium to ensure your 1970s algorithms feel exactly as cramped as they did 55 years ago.



Visual Evidence from the Workbench


SCREENSHOT: DCL + SRC + WRM/RDM flow in Quadium
asm00.jpg
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ram00.jpg
ram00.jpg (13.54 KiB) Viewed 53 times

In the screenshot, you can see bank selection (DCL), address-context setup (SRC), and the following RAM operation (WRM/RDM or WRx/RDx).

Code: Select all

; Minimal RAM write on 4004
; bank=0, chip=1, reg=2, char=3, value=A
        LDM 0          ; ACC=0
        DCL            ; select RAM bank 0
        LDM 6          ; 4*chip + reg = 4*1 + 2
        XCH R12        ; high nibble for SRC
        LDM 3          ; char index
        XCH R13        ; low nibble for SRC
        SRC 6P         ; select chip/reg/char
        LDM 10         ; value A
        WRM            ; write RAM char
END:    JUN END        ; stop here


If modern CPUs answer questions with a single instruction, the 4004 answers with a choreography — and once you learn the steps, it stops feeling primitive and starts feeling deliberate.